Field of the Invention
The invention relates to a semiconductor memory device and a programming method thereof, and to error checking and correction of input/output data of the semiconductor memory device. More particularly, the invention relates to error checking and correction of input data of a NAND flash memory.
Description of Related Art
The degree of integration of semiconductor memories such as flash memory, dynamic random access memory (DRAM) and so on is increasing year by year, thus making it difficult to manufacture a memory element free of failure or defect. Accordingly, with respect to a memory chip, a redundancy scheme for remedying a physical defect in appearance of the memory element caused during a manufacturing process is adopted. For example, in a certain redundancy scheme, the memory element having a physical defect is remedied by disposing a redundant memory. Moreover, in a semiconductor memory, in addition to the physical remedy by the redundant memory, an error checking correction (ECC) circuit is used as a soft error countermeasure.
In a NAND flash memory, due to repeated programming or erasure of data, a charge keeping characteristic deteriorates as a result of degradation of a tunnel insulating film, or threshold variation occurs due to a charge trapped by the tunnel insulating film, leading to a bit error. Patent Document 1 discloses loading an ECC circuit as such soft error countermeasure. Especially in a memory cell close to a block selecting transistor, there is a trend of increasing bit error rate as a result of uneven patterns caused by lithography or uneven ion implantation during formation of a diffusion layer. Thus, an ECC code is stored for remedying more of such bit errors.
Moreover, among NAND flash memories, there are not only NAND flash memories in which one memory cell stores 1-bit data, but also NAND flash memories in which one memory cell stores multi-bit data. Patent Document 2 discloses an error correction scheme for such multi-bit data. Further, Patent Document 3 discloses a flash memory as follows. An error checking correction (ECC) parity is added to inputted data to generate an ECC code, and the generated ECC code is written to a physical block. When there is an error in page data read from the physical block, the ECC code is utilized to correct the error. The physical block having a number of corrected errors equal to or greater than a threshold is registered in a table as a warning block. During data writing, the priority of the warning block for selection is lowered.